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Lattice Semiconductor
Detailed Register Descriptions (Continued)
(0x)
CSIX-to-PI40 IP Core User’s Guide
Absolute
Reset Value
Address
Bit
Name
(0x)
Description
Out_Cntrl_Hi_Watermark_xx (Read/Write), xx = [0, 1]
805C - 0
[0:7]
OBC_HI_WMARK_xx
3f
Channel xx, high watermark for outbound control FIFO. This
809C - 1
value represents the number of FIFO words (4 bytes) that
assert the FIFO high watermark. When the number of words
in the FIFO exceeds this value, the FIFO’s partial_full signal
asserts.
FIFO Under?ow Error Register (clear on read)
8140
[0:5]
[6]
Not Used
UF_ERR_1
n/a
Not Used
When high, indicates that one of the FIFOs for channel 1
experienced an under?ow error. The associated channel’s
FIFOs should be ?ushed to guarantee proper operation after
the under?ow. This bit clears upon reading. If the stimulus that
caused the error is removed, then the error bit in this register
will clear after reading.
[7]
UF_ERR_0
When high, indicates that one of the FIFOs for channel 0
experienced an under?ow error. The associated channel’s
FIFOs should be ?ushed to guarantee proper operation after
the under?ow. This bit clears upon reading. If the stimulus that
caused the error is removed, then the error bit in this register
will clear after reading.
FIFO Over?ow Error Register (clear on read)
8144
[0:5]
[6]
Not Used
OF_ERR_1
n/a
Not Used
When high, indicates that one of the FIFOs for channel 1
experienced an over?ow error. The associated channel’s
FIFOs should be ?ushed to guarantee proper operation after
the under?ow. This bit clears upon reading. If the stimulus that
caused the error is removed, then the error bit in this register
will clear after reading
[7]
OF_ERR_0
When high, indicates that one of the FIFOs for channel 0
experienced an over?ow error. The associated channel’s
FIFOs should be ?ushed to guarantee proper operation after
the under?ow. This bit clears upon reading. If the stimulus that
caused the error is removed, then the error bit in this register
will clear after reading
Parity Error Register (clear on read)
8148
[0:1]
[2]
Not Used
VPERR_1
n/a
Not Used
When high, indicates that a vertical parity error occurred on
the inbound CSIX port for channel 1. This bit clears upon
reading. If the stimulus that caused the error is removed, then
the error bit in this register will clear after reading
[3]
[4:5]
[6]
[7]
VPERR_0
Not Used
HPERR_1
HPERR_0
When high, indicates that a vertical parity error occurred on
the inbound CSIX port for channel 0. This bit clears upon
reading. If the stimulus that caused the error is removed, then
the error bit in this register will clear after reading
Not Used
When high, indicates that a horizontal parity error occurred on
the inbound CSIX port for channel 1. This bit clears upon
reading. If the stimulus that caused the error is removed, then
the error bit in this register will clear after reading.
When high, indicates that a horizontal parity error occurred on
the inbound CSIX port for channel 0. This bit clears upon
reading. If the stimulus that caused the error is removed, then
the error bit in this register will clear after reading.
15
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